1. Field of the Invention
The present invention relates to a master clock input circuit for amplifying and outputting a master clock input from an oscillator, or the like, when a mode signal is at an active level.
2. Description of Related Art
A master clock input circuit is a circuit for amplifying a master clock signal (frequently called simply “master clock” hereafter) generated by an oscillator, or the like. The amplified clock is used as an operational clock for another integrated circuit formed within a semiconductor chip.
An integrated semiconductor circuit capable of switching between a normal mode and a low-current-consumption mode for each respective circuit block is already known. When a circuit block is not required to operate, in other words, when the block is at standby, it is set to low-current-consumption mode. On the other hand, when it operates, the circuit block switches to normal mode. By setting a circuit block to low-current-consumption mode when it is not operating, it is possible to restrict the power consumption of the circuit block.
In an integrated circuit of this kind, a master clock input circuit is provided for each circuit block. Thereby, an operational clock is supplied from a corresponding master clock input circuit to a circuit block that is set to normal mode. On the other hand, an operational clock is not supplied from a corresponding master clock input circuit to a circuit block that is set to low-current-consumption mode. Thereby, it is possible to restrict the power consumption of the master clock input circuit.
In a general integrated circuit, respective master clock circuits are connected to the same oscillator. Therefore, if noise is generated at the input side of any one of the master clock input circuits, then that noise will be superimposed on the master clock output by the oscillator, and hence there is a risk that it may be input to other master clock input circuits. Noise input to a master clock input circuit degrades the waveform of the operational block output by the master clock circuit during normal mode. This degradation may be a cause of malfunction of the circuit block. Input-side noise is liable to occur when switching between normal mode and low-current-consumption mode.